The present invention relates to a display device of a television receiver or the like using the CRT, and more particularly to a digital image correction device for correcting convergence and graphic distortion on the screen, and a display device comprising such digital image correction device.
FIG. 1 is a block diagram showing a structural example of a conventional digital image correction device disclosed in Japanese Patent Application Laid-open No. 7-288830. This digital image correction device comprises an input terminal 1 for receiving a horizontal blanking pulse, an input terminal 2 for receiving a vertical blanking pulse, a phase locked loop (PLL) 3 and a field judging circuit 7 connected to the input terminals 1, 2, a dividing counter 4 receiving a reference clock from the PLL 3, and an H address counter 5 connected to the input terminal 2 for receiving a system clock from the dividing counter 4.
This digital image correction device further comprises a memory 6 connected to the H address counter 5, a latch circuit 8 connected to the memory 6, an average calculation circuit 9 connected to the memory 6 and latch circuit 8, and a switch circuit 10 connected to the memory 6, average calculation circuit 9, and field judging circuit 7.
The digital image correction device also comprises a latch circuit 11 connected to the switch circuit 10, a digital/analog converter (D/A converter or DAC) 12 connected to the latch circuit 11, a low pass filter (LPF) 13 connected to the D/A converter 12, an amplifier (AMP) 14 connected to the LPF 13, and a convergence yoke coil (CY coil) 15 connected to the amplifier 14.
In thus constituted digital image correction device, the operation is described below.
In advance, the convergence correction amount required at each point on the screen as shown in FIG. 2B is stored as convergence correction data in the memory 6 (0000, 0001, . . . ; address) in the unit of 1 byte as shown in FIG. 2A. In synchronism with raster scanning in the CRT, the convergence correction data of each point is read out sequentially from the first horizontal scanning line on the screen. The convergence correction data being read out is converted into analog data in the D/A converter 12, and data are interpolated by the LPF 13 to be a continuous convergence correction signal, which is amplified by the amplifier 14 to drive the CY coil 15.
As a result, in the CRT, the convergence correction magnetic field for correcting the convergence at each point on the screen is generated from the CY coil 15.
From the input terminal 1, a horizontal blanking pulse H. BLK of horizontal deflection frequency fH synchronized with raster scanning in the CRT is fed, and from the input terminal 2, a vertical blanking pulse V. BLK of vertical deflection frequency fV synchronized with raster scanning in the CRT is fed.
The PLL 3 generates a reference clock of the multiplied horizontal blanking pulse H. BLK, and the dividing counter 4 supplies the H address counter 5 with a system clock for always keeping constant the frequency division in the horizontal direction in synchronism with the reference clock.
The H address counter 5, receiving the vertical blanking pulse V. BLK, generates a read address corresponding to the horizontal and vertical time phase (corresponding to the position on the screen).
Accordingly, the convergence correction amount required at each point (convergence correction point) necessary for convergence correction on the screen can be individually controlled, and a convergence correction signal having a specified waveform can be obtained.
The field judging circuit 7 receives the horizontal blanking pulse H. BLK from the input terminal 1, and the vertical blanking pulse V. BLK from the input terminal 2. From the phase relation of the horizontal blanking pulse H. BLK and vertical blanking pulse V. BLK, the field judging circuit 7 judges odd and even fields, and controls the switch circuit 10 depending on the judging result.
The switch circuit 10 closes to the X side in the case of even field, and to the Y side in the case of odd field.
In the memory 6, on the other hand, only the convergence correction data of a convergence correction point on the even field screen is stored preliminarily. The convergence correction data read out from the memory 6 is supplied to the X side of the switch circuit 10 and the latch circuit 8.
In the latch circuit, the supplied convergence correction data is delayed by one horizontal period. The convergence correction data output from the latch circuit 8 is supplied to the average calculation circuit 9, and the average with the convergence correction data being read out by delay of two horizontal periods from the memory 6 is calculated.
Accordingly, the convergence correction data supplied simultaneously to the average calculation circuit 9 are convergence correction data at individual convergence correction points in two adjacent horizontal scanning lines of the even field, and hence their average convergence correction data is obtained. This averaged convergence correction data is fed to the Y side of the switch circuit 10.
Therefore, in the even field, the convergence correction data being read out from the memory 6 directly passes through the switch circuit 10, and is sequentially latched by the latch circuit 11, and in the case of odd field, by the switch circuit 10, the averaged convergence correction data from the average calculation circuit 9 is selected as the convergence correction data of odd field, and is sequentially latched by the latch circuit 11.
The convergence correction data output from the latch circuit 11 is converted into analog convergence correction data by the D/A converter 12, and data are interpolated by the LPF 13 to be continuous convergence correction signal, which is amplified by the amplifier 14 and is supplied into the CY coil 15.
Thus, according to the prior art, the convergence correction data only in the even field out of odd and even fields, is stored in the memory 6. In the odd field, the convergence correction data at convergence correction points in adjacent two horizontal scanning lines in the even field are averaged to obtain convergence correction data, and therefore the memory 6 is reduced in necessary capacity as compared with the case of storing all convergence correction data in the odd and even fields preliminarily in the memory 6.
The same holds true also in other operations than convergence correction, and in graphic distortion correction, white balance and uneven luminance correction, and focus correction, individually, correction data of graphic distortion, correction data of white balance and uneven luminance, and correction data of focus are stored in the memory, and each correction is performed by installing the graphic distortion correction circuit, white balance and uneven luminance correction circuit, or focus correction circuit, instead of the magnetic field generating circuit for convergence correction (amplifier 14, CY coil 15).
In the conventional digital image correction device, as mentioned above, since a circuit for reducing the necessary capacity of the memory 6 is needed, the circuit composition is complicated, and when the number of horizontal scanning lines is changed, that is, when the frequency of the synchronizing signal is changed, there was a limit in the memory capacity for storing the correction data to be supplied corresponding to the increased horizontal scanning lines in order to keep the precision of correction, and there were also other cost problems by the constitution.
Moreover, to enhance the correction precision, it is necessary to raise the resolution of the signal fed into the D/A converter, but when this resolution is raised, a more expensive D/A converter is needed, and the number of bits per correction data stored in the memory increases, and a more expensive memory is required, which causes to raise the cost of the digital image correction device.